1. Technical Field
Various embodiments of the present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus including an input/output circuit.
2. Related Art
A semiconductor apparatus is loaded on a test equipment and various tests are performed to check the normal operation and the operation characteristics of a product.
The operation speed and calculation capability of an electronic system are gradually augmented. Accordingly, demand for a higher speed semiconductor apparatus has been increased. As a semiconductor apparatus gradually operates at a higher speed, the operation speed of a semiconductor apparatus has exceeded the supportable limit speed of test equipments. Thus, it is often conceivable that the higher speed semiconductor apparatus cannot be tested for high speed operations in the contemporary test equipment. In other words, a semiconductor apparatus manufactured to operate at a high speed (hereinafter, referred to as a “high speed semiconductor apparatus”) can be checked only for operation characteristics to the supportable limit speed of the contemporary test equipment for testing a semiconductor apparatus operating at a low speed (hereinafter, referred to as a “low speed test equipment”). Accordingly, it is necessary to invest in novel high speed test equipments capable of performing tests for the high speed operations of the high speed semiconductor apparatus. However, the investment in the new high speed test equipment requires huge costs, which in turn influences the manufacturing cost and the productivity of a semiconductor apparatus.
If it is possible to load and test the high speed semiconductor apparatus on the low speed test equipment, the necessity of the investment in novel high speed test equipments can be substantially lessened, and the manufacturing cost of a semiconductor apparatus can be reduced. Also, the capability of loading the high speed semiconductor apparatus on both the low speed test equipment and a high speed test equipment contributes to an increase in the productivity of a semiconductor apparatus. Accordingly, a high speed semiconductor apparatus capable of being tested on both the low speed test equipment and the high speed test equipment has been demanded in the art.
In a semiconductor memory apparatus such as a DRAM, the following problems exist in loading a high speed semiconductor memory apparatus on a low speed test equipment and testing the high speed operations of the high speed semiconductor memory apparatus.
First, the low speed test equipment cannot provide the high speed semiconductor memory apparatus with a high speed external clock necessary to ensure high speed operations. The external clock is inputted to an internal delay locked loop (DLL) circuit and is used to generate a DLL clock (CLK_DLL) for controlling a data output timing, and is inputted to an internal command generation circuit and is used to generate internal active, read and write commands and various timing signals responding to the internal commands.
Second, the low speed test equipment is incapable of providing data at a high speed to the high speed semiconductor memory apparatus. That is to say, not only the speed of the external clock which is provided to the high speed semiconductor memory apparatus by the low speed test equipment is low, but also the speed at which the low speed test equipment inputs data to the high speed semiconductor memory apparatus is low.
Third, the low speed test equipment is incapable of normally receiving the data which is outputted at a high speed by the high speed semiconductor memory apparatus. In order to ensure data exchange between a test equipment and a semiconductor memory apparatus, timing match should be implemented between data and a data strobe signal (DQS). In general, since the speed of transition of the logic value of the data received by the test equipment is set to match the speed of the external clock which is inputted to the semiconductor memory apparatus by the test equipment, the low speed test equipment cannot normally sense the transition of the logic value of the data outputted by the high speed semiconductor memory apparatus which operates at a speed higher than the speed of the external clock inputted to the semiconductor memory apparatus.
Fourth, the low speed test equipment is incapable of normally receiving the data strobe signal which is outputted at a high speed by the high speed semiconductor memory apparatus. As mentioned in the third reason why the low speed test equipment cannot load the high speed semiconductor memory apparatus and perform tests at a high speed, the low speed test equipment is incapable of normally sensing the transition of the logic value of the data strobe signal outputted by the high speed semiconductor memory apparatus which operates at a speed higher than the speed of the external clock inputted to the semiconductor memory apparatus.